1. Field of the Invention
The present invention relates to a direct memory access control apparatus, and more specifically to such a direct memory access control apparatus that is adapted for data transfer between an electronic cash register, for example, and an external high speed input/output device without the active participation of a central processing unit.
2. Description of the Prior Art
A data collecting apparatus for collecting data registered in an electronic cash register by transferring the same to an external storage device is conventionally known. Such an external storage device may comprise a high speed input/output device such as a floppy disk, magnetic cassette storage, cartridge magnetic disk, or the like. A one-chip microcomputer is utilizied as a central processing unit for controlling the high speed input/output device. However, it is known that the processing speed of a one-chip microcomputer is relatively slow. Therefore, in transferring data between a high speed input/output device and an electronic cash register on a byte-by-byte basis, the processing operation of the central processing unit cannot follow the high speed input/output device. Although this problem can be solved by employing a high speed microcomputer, suitable high speed microcomputers are expensive. Therefore, in order to perform such data transfer, a direct memory access system for performing direct data transfer between a memory and a high speed input/output device without direct control by the interposition of a central processing unit has been conventionally proposed.
FIG. 1 is a block diagram of a known data collecting apparatus for performing data transfer between an electronic cash register and a high speed input/output device. Referring to FIG. 1, the data collecting apparatus in accordance with a conventional direct memory access system will be described. An electronic cash register 10 is connected to an electronic cash register interface 20 and the electronic cash register interface 20 is connected to a direct memory access control portion 30. A high speed input/output device 40 is connected to the direct memory access control portion 30. The direct memory access control portion 30 comprises a central processing unit and memory, which are coupled to each other by means of a data bus and an address bus. Upon receipt of a direct memory access request from the high speed input/output device 40, the central processing unit is placed in a floating state, in which it is not capable of communication with the memory. While the central processing unit is in the floating state, the direct data transfer, i.e. direct memory access transfer is performed between the high speed input/output device 40 and the memory.
According to such a conventional data collecting apparatus, since the central processing unit is placed in a floating state during direct memory access transfer, even if an interrupt signal is received at that time, the interrupt signal will be ignored and processing for that interrupt will not be preformed. More specifically, if an interrupt signal for clearing the contents in the memory upon turning off of a power supply, for example, is received by the central processing unit during the direct memory access transfer, the central processing unit will not respond. Therefore, there is no possibility that the contents of the memory will be erased. On the other hand, if an interrupt signal is received from the electronic cash register 10, the interrupt signal is also disregarded and hence any required processing cannot be performed. This can have detrimental results in that the cash register may not perform properly. Furthermore, if a HALT request signal is received while an interrupt processing operation is being performed after the central processing unit completed the direct data transfer, the interrupt processing operation is suspended.
In order to solve these problems, another system referred to as a cycle steal direct memory access system has been proposed for the central processing unit. The cycle steal direct memory access system is designed to perform direct memory access transfer on a byte-by-byte basis in accordance with a dummy cycle for each command stored in a read only memory. Although the cycle steal direct memory access system enables the central processing unit itself to perform other processing even during direct memory access transfer, another problem arises in that the time required for the data transfer to be completed is lengthened.